1. Field of the Invention
The present invention relates generally to semiconductor circuit devices and particularly to semiconductor output circuit devices reliably generating an output signal at high speed.
2. Description of the Background Art
Semiconductor devices such as semiconductor memory devices and semiconductor logic processing devices need to use a bus for transmitting and receiving signals/data between devices. The bus signal line, provided external to the devices, has a large lord. In order to drive the external signal line at high speed for transferring a signal/data, these semiconductor devices are each provided with an output circuit formed of a transistor having a large driving capability. With an output circuit for transferring a signal/data, the bus signal line needs to be driven to an H (logical high) level or an L (logical low) level depending on the signal/data to be transmitted.
FIG. 9 shows an exemplary configuration of a conventional semiconductor output circuit, and representatively shows a configuration of a data output circuit outputting data DQ. In FIG. 9, the semiconductor output circuit includes an output drive control circuit 100 for generating data output control signals DQH and DQL according to internal data, an inverter 102 for inverting output control signal DQH to generate a complementary output control signal /DQH, and an output buffer circuit 104 driving an output node 104a in accordance with the signal /DQH output from inverter 102 and output control signal DQL.
Output control signals DQH and DQL are generated in accordance with a data output timing signal and internal data. In outputting data, when internal output data is at an H level, output control signals DQH and DQL are set to the H and L levels, respectively, and when internal output data is at an L level, output control signals DQH and DQL are set to L and H levels, respectively. When data is not output, output drive control circuit 100 sets output control signals DQH and DQL both to the L level in accordance with the data output timing signal.
Output buffer circuit 104 includes a p channel MOS transistor (an insulated gate field effect transistor) Q71 connected between a power supply node receiving a power supply voltage VDD and output node 104a and having a gate receiving signal /DQH output from inverter 102, and an n channel MOS transistor Q72 connected between output node 104a and a ground node and having a gate receiving output control signal DQL. P channel MOS transistor Q71 has a backgate connected to the power supply node.
In the configuration of the semiconductor output circuit configuration shown in FIG. 9, when output control signals DQH and DQL are both at the L level, MOS transistors Q71 and Q72 are both in the OFF state (non-conductive state), and output buffer circuit 104 is in an output high impedance state.
When output control signal DQH is at the H level and output control signal DQL is at the L level, inverter 102 outputs signal /DQH of the L level and in output buffer circuit 104, MOS transistors Q71 and Q72 are set in the ON state (conductive state) and OFF state, respectively, and output node 104a is driven to the power supply voltage VDD level via MOS transistor Q71.
When output control signals DQH and DQL are at the L and H levels, respectively, MOS transistors Q71 and Q72 in output buffer circuit 104 enter the OFF and ON states, respectively, and output node 104a is driven to the ground voltage level via MOS transistor Q72 and output data DQ attains the L level.
A CMOS buffer circuit configured of p- and n-channel MOS transistors Q71 and Q72, as shown in FIG. 9, can be used to drive output node 104a to the power supply voltage VDD level and the ground voltage level.
If such an output buffer circuit is used, output node 104 accompanies a lord such as an external signal line and a lead terminal. Therefore, in order to drive the signal/data at output node 104a to the power supply voltage VDD level or the ground voltage level, some transition period of time is required. If this transition period of time is reduced by increasing the current supplying capability of output buffer circuit 104, parasitic inductance on output node 104a causes ringing of overshoot/undershoot and the signal/data cannot be transferred at high speed. Therefore, there is a limit value for a transition period of time output signal.
Furthermore, as will be described below, output data might vary in amplitude depending on an output data pattern, or on a sequence of H- and L-level signals. Specifically, as indicated in FIG. 10 by a solid line LA, when two data of the same logic level and two data of another common logic level are alternately outputted in a unit of the two data, such as in a sequence of H level data, the H level data, the L level data and the L level data, the driving time of the output node by output buffer circuit 104 in one direction is increased, and there is caused a case where an output signal varies exceeding an H side voltage level VH and a L side voltage level VL.
When output data at the H level and data at the L level are output alternately, the output node is driven in one direction for a reduced period of time. As indicated in FIG. 10 by a broken line LB, the output signal makes a transition within the H side voltage level VH and the L side voltage level VL.
Therefore, even if output data are transferred at the same frequency, the output data may vary in amplitude, depending on the data pattern to be transferred. Thus, a subsequent circuit possibly may inaccurately determine the logic level of the received data, and the data cannot be transferred at high speed. In this case, output data transitioning from H level to L level and that transitioning from L level to H level may attain an intermediary voltage level (an input logic threshold voltage level for the subsequent circuit) in different periods of time, and consequently, the subsequent circuit would have a reduced timing margin for an input signal.
Furthermore, if output data differ in frequency, signal amplitude differ similarly, and in fast data transfer, the output node comes to be driven for a reduced period of time and the output data is reduced in amplitude, while in a slow operation, the output node is driven for an increased period of time and the output data is increased in amplitude.
Furthermore, if output data of a common logic level is output successively in data pattern, an amplitude of output data would be deviated toward the H or L level, as shown in FIG. 11.
Specifically, in FIG. 11, a solid line LC represents a signal waveform in a case when data of the L level continue and data of the H level is then output, and a broken line LD represents a signal waveform in a case when data of the H level are successively read and data of the L level is then read.
For example, if data/signal of the L level continue, the data/signal transitions down to the ground voltage GND level and then to the H level, and therefore, the signal/data would vary between H-side voltage VH and ground voltage GND, as indicated in FIG. 11 by solid line LC. In contrast, if data of the H level continue, the signal/data would vary between L-side voltage VL and power supply voltage VDD, as indicated in FIG. 11 by broken line LD.
As shown in FIG. 11, if an output signal/data of the H level and an output signal/data of the L level are different in amplitude (with respect to an input logic threshold voltage Vcr of a subsequent stage), the subsequent circuit cannot take in an input signal accurately. Consequently, a margin for the input logic threshold voltage varies and an input circuit of the subsequent circuit would make an erroneous decision on H level/L level of input data.
Thus, in order to reliably transfer data/signal at high speed, it is required to transfer a signal/data transitioning in the same amplitude with the input logic threshold voltage Vcr of the subsequent circuit being the center. Particularly, by transferring a signal smaller in amplitude than power supply voltage VDD through amplitude limitation, charging and discharging current of an external signal line can be reduced, and consequently, power consumption can be advantageously reduced, in addition to the advantage of fast transfer of data/signal.
FIG. 12 schematically shows a configuration of a conventional semiconductor circuit device. In FIG. 12, a semiconductor circuit device 110 includes a semiconductor circuit 112 performing a predetermined process to generate output control signals DQL and /DQH, and an output buffer circuit 114 generating output data DQ in accordance with output control signals /DQH and DQL of semiconductor circuit 112. Output buffer circuit 114 includes a p channel MOS transistor Q91 pulling up an output node in accordance with output control signal /DQH and an n channel MOS transistor Q92 pulling down the output node in accordance with output control signal DQL.
Semiconductor circuit 112 receives power supply voltage VDD through a power supply terminal 115 and ground voltage VSS through a ground terminal 116. Output buffer circuit 114 receives a high-side output power supply voltage VDDQ though an output power supply terminal 117 and a low-side output power supply voltage VSSQ through a power supply terminal 118.
Power supply voltage VDDQ and VSSQ are different in level from power supply voltage VDD and VSS supplied to semiconductor circuit 112, respectively. Specifically, output power supply voltage VDDQ is at a level lower than power supply voltage VDD and output power supply voltage VSSQ is at a level higher than ground voltage VSS. By supplying power supply voltage VDDQ and VSSQ dedicatedly to the output circuit, output buffer circuit 114 can output data DQ having an amplitude smaller than power supply voltage VDD. Furthermore, whatever pattern output data may have, an output signal can be prevented from having a voltage level shifted in one direction.
Semiconductor circuit device 110 is assembled on a substrate or board limited in the kinds of power sources. Thus, there is caused a problem that it is difficult to supply power supply voltages VDDQ and VSSQ exclusively to the output circuit. Therefore, output buffer circuit 114 cannot receive power supply voltages VDDQ and VSSQ of an optimized voltage level and, as described with reference to FIG. 11, signal waveform distortion and H level/L level amplitude deviation are caused and data/a signal cannot be transferred reliably at high speed. It is thus necessary to limit an amplitude of output signal/data while maintaining power supply voltage level.
FIG. 13 shows a configuration of a data output portion of a conventional semiconductor circuit having an amplitude limiting function. In FIG. 13, a semiconductor circuit device 120 includes an output buffer circuit 122 driving an output node 125 in accordance with output control signals /DQH and DQL, and an amplitude limiting circuit 124 for limiting the amplitude of data DQ output from output node 125. These output buffer circuits 122 and 124 receive power supply voltage VDD as one operating power supply voltage and ground voltage GND as the other power supply voltage.
Output buffer circuit 122 includes a p channel MOS transistor Q1a pulling up the voltage of output node 125 in accordance with output control signal /DQH, and an n channel MOS transistor Q2a pulling down the voltage of output node 125 in accordance with output control signal DQL.
Amplitude limiting circuit 124 includes a resistance element RH connected between a power supply node and output node 125, and a resistance element RL connected between output node 125 and a ground node.
In the semiconductor circuit device shown in FIG. 13, when output control signals /DQH and DQL both are at the L level, output node 125 is supplied with current via MOS transistor Q1a. The current supplied through MOS transistor Q1a and resistance element RH is discharged to the ground node through resistance element RL. Thus, the H level data has a voltage V (H), as represented in the following expression:V(H)=RL·VDD/(ON(Q1a)//RH+RL),where ON (Q1a) represents the channel resistance of MOS transistor Q1a. Resistance element RL has a resistance value represented by the same reference character RL. The symbol “//” represents a parallel combined resistance of the channel resistance (or ON resistance) ON (Q1a) of MOS transistor Q1a and resistance element RH.
When output control signals /DQH and DQL both are at the H level, output node 125 is discharged via MOS transistor Q2a to the ground voltage level. In this case, current is discharged from resistance element RH through MOS transistor Q2a and resistance element RL to the ground node. Thus, when the L level data is generated, output node 125 is at a voltage V (L), as represented in the following expression:V(L)=(ON(Q2a)//RL)·VDD/(RH+ON(Q2a)//RL),where ON (Q2a) represents the channel resistance of MOS transistor Q2a. 
In order to set the output voltage V (H) and V (L) at a voltage level between power supply voltage VDD and the ground voltage with resistance elements RH and RL, resistance elements RH and RL need to be made substantially the same in resistance value as the channel resistance (ON resistance) of the MOS transistors Q1a and Q2a. Typically, outputting MOS transistors Q1a and Q2a have channel resistance (ON resistance) of several tens Ω. If resistance elements RH and RL have a value in resistance of approximately the same level, this output portion would constantly cause a through-current of several tens mA to flow through resistance elements RH and RL. That is, irrespective of whether or not data output is performed, amplitude limiting circuit 124 constantly flows the through-current, and current consumption, standby current in particular, would disadvantageously be increased. In particular, if this semiconductor circuit device is a semiconductor memory device and outputs multibit data, the though-current further increases and semiconductor memory device cannot operate with low standby current.
Furthermore, the ON resistances of MOS transistors Q1a and Q2a and the resistance values of resistance elements RH and RL vary if a process parameter varies in the manufacturing process. When the ON resistances of outputting MOS transistors Q1a and Q2a and the resistance values of resistance elements RH and RL vary, output data DQ accordingly varies in amplitude, and a signal having a small, constant amplitude is hardly generated.
Furthermore, if output node 125 connects with different loads for different system configurations, data from output node 125 differ in amplitude for different systems accordingly.
FIG. 14 shows still another configuration of the output portion of the conventional semiconductor circuit device. In FIG. 14, semiconductor circuit device 130 includes an output buffer circuit 132a for driving an output node 132a in accordance with output control signals /DQH and DQL, and a current limiting resistance element RS connected between output node 132a and an external signal line 140.
External signal line 140 is coupled with a terminating voltage source 142 through a terminating resistance element RT. Terminating voltage source 142 supplies an intermediate voltage VDD/2.
In the configuration shown in FIG. 14, when MOS transistor Q1b is in an ON state, current flows to terminating voltage source 142 through MOS transistor Q1b, resistance element RS and terminating resistance RT. Thus, when data DQ is at the H level, the H level data has a voltage level V (DQH), as represented in the following equation:V(DQH)=VDD·RT/2·(ON(Q1b)+RS+RT)+VDD/2,where ON (Q1b) represents the channel resistance (or ON resistance) of MOS transistor Q1b. 
When MOS transistor Q2b is in the ON state, current flows from terminating voltage source 142 though resistance elements RT and RS and MOS transistor Q2b to the ground node. Thus, when data DQ is at the L level, the data has a voltage level V (DQL), as represented in the following expression:V(DQL)=VDD·(ON(Q2b)+RS)/2(ON(Q2b)+RS+RT),wherein ON (Q2b) represents the channel resistance (or ON resistance) of MOS transistor Q2b. 
As in the configuration shown in FIG. 14, when terminating resistance RT is used to provide output data DQ smaller in amplitude than power supply voltage VDD, resistance elements RS and RT need to be substantially the same in resistance value as the ON resistance of MOS transistors Q1b and Q2b. Thus, terminating resistance RT conducts relatively large current flow.
Furthermore, when the ON resistance of MOS transistors Q1b and Q2b are significantly varied, due to the variation in process parameter in a manufacturing process, operation temperature, or power supply voltage, as compared with the resistance elements RT and RS, output data DQ significantly varies in amplitude, as described below.
Specifically, for manufacturing parameter variation, the MOS transistor has an ON resistance varying in a range of approximately ±10 to 20%. In addition, as to the variation of ON resistance of MOS transistor for the operation temperature variation, the ON resistance of MOS transistor varies in a range of approximately ±8 to 16% for a temperature variation of 100° C. Furthermore, for a variation in power supply voltage of ±10%, the ON resistance of MOS transistor varies in a range of approximately ±10 to 15%. When these variation factors are all taken into account, the MOS transistor has an ON resistance varying in a range of approximately ±28 to 51%.
From the above expressions, output data DQ has an amplitude of V (DQH)−V(DQL), as represented by the following equation:V(DQH)−V(DQL)=VDD·RT/(ON(Q2b)+RT+RS),where MOS transistors Q1b and Q2b are assumed to be equal in ON resistance. When the MOS transistor has its ON resistance varied, output data also varies in amplitude. If such variation factors as described above cause the ON resistance of MOS transistor to vary to increase output data in amplitude, data cannot be transferred at high speed and current consumption also increases disadvantageously.
Furthermore, if semiconductor circuit device 130 is a semiconductor memory device and outputs, as data DQ, data of as many as 64 bits, terminating voltage source 142 is required to supply terminating voltage VDD/2 to the 64 bits of data in common. In this context, if the 64-bits as many of data vary in a single direction, several hundreds mA of current would be consumed. Accordingly, while such current is consumed in the output circuits, the voltage level of terminating voltage VDD/2 is required to be held constant, and a severe requirement is imposed on terminating power supply source 142.
In particular, if a terminating voltage source is formed of a simple voltage dividing circuit, the terminating voltage source would accompany an increased through-current, which is unsuitable for low power consumption systems. There arises a problem that it is difficult to configure a terminating power source with a small occupation area, small power consumption and great current supplying capability.
Thus, according to the configuration of an output circuit in a conventional semiconductor circuit device, an output signal/data of a small amplitude could not transferred at high speed stably with small power consumption.